Sequence ""Zero Simulation"" Key to Low-Power RTL Design
High-Level Power Preview With NanoCool Flow
SANTA CLARA, Calif.--(BUSINESS WIRE)--May 20, 2002--Sequence
Design today announced the incorporation of new capabilities in
PowerTheater(TM) that allow front-end designers to estimate power
consumption at the RTL level using static vector-independent analysis,
without test benches or simulation.
Part of the company's NanoCool(TM) flow for low-power, low-voltage
100nm SoC design, PowerTheater's Zero-Sim, for "zero simulation,"
feature provides intelligent feedback on average power consumption
early, and at successive iterations, to optimize power before freezing
RTL code.
"Having the ability to perform a fast power estimate is important
in the early micro-architectural stages of RTL design where
significant power savings can be achieved," said Dr. Ted Williams,
vice-president of silicon engineering at MorphICs Technology. "This
directly shows the effect on power consumption of RTL modifications,
confidently covering all possible stimulus cases."
Rather than providing a difficult-to-control automatic power
optimization, PowerTheater gives the user flexibility by presenting an
"RTL power cockpit." In this RTL low-power design environment, a
comprehensive view of power tradeoffs and recommendations for power
reduction are presented. With a straightforward GUI for the input of
basic parameters to receive immediate estimates, users can make
intelligent decisions affecting power consumption on the fly. Based on
the level of detail offered, PowerTheater provides accurate scenarios
for various design tradeoffs impacting average power consumption.
"Precisely estimating power is critical for its management as the
design matures," said William Ruby, Sequence director of product
marketing for low-power design. "This issue has been a design
conundrum. In order to design a test bench for power, designers had to
finalize RTL code, but that severely limited changes. Sequence appears
to be the only company that can save designers time by eliminating
simulation, while insuring the confidence in results our customers
have come to expect."
"PowerTheater is a central component of our NanoCool initiative
for low-voltage nanometer design," according to Vic Kulkarni, Sequence
chief operating officer. "In addition to the "Zero-Sim" capability we
are announcing today, we also recently added IP modeling for power to
the product suite. We have seen solid market momentum for this suite
as low-power design becomes critical for both fixed and mobile
communications ICs."
About PowerTheater
PowerTheater is a comprehensive power management design suite that
includes accurate RTL and gate-level full-chip power analysis and
flexible power optimization. PowerTheater has market momentum with
users such as Sun and Silicon Metrics, and is integrated into IBM's
Blue Logic(TM) ASIC design system. By providing accurate RTL power
estimation, precise gate-level power verification, and flexible power
optimization, PowerTheater helps designers minimize power early in the
design cycle and verify that power budgets are met. A versatile
graphical analysis environment lets designers assess tradeoff options
quickly and intuitively, along with full-chip analysis covering all
major contributors to power dissipation.
NanoCool Initiative
Sequence has assembled the elements of a low-power/low-voltage
flow spanning architectural, logical, and physical design to respond
to the challenges of ultra-DSM environments under its NanoCool
initiative, a partnership between semiconductor designers, EDA tool
vendors, IP companies, and library suppliers, to offer a complete flow
offering concurrent power management, timing and signal integrity
capabilities to achieve rapid design closure at 130 nm and below.
Partners include Circuit Semantics, Silicon Metrics, and Virtual
Silicon.
Sequence's leadership position in power, noise and timing
optimization, and high accuracy extraction form the foundation for
this initiative. On top of this foundation, Sequence is building the
next generation of EDA capabilities that are specifically targeted at
low-voltage, nanometer problems such as minimization of both dynamic
and leakage currents, noise margin analysis and optimization, and
reliability verification. Low-voltage scaling has always been
considered an anathema in terms of analog circuit performance. But
even digital experts are recognizing that increases in leakage
currents and decreases in noise margins are resulting in noisy power
hogs in portable systems. The overall focus of Sequence's efforts will
be the concurrent analysis and optimization of power, timing, and
noise. The initiative will include both high-level prediction and
optimization coupled with successive refinements and optimizations at
lower levels to help designers achieve design closure.
The key components of the NanoCool flow are:
- Architectural Exploration for Power Reduction
- IP Power Modeling
- Zero-Sim Average Power Analysis
- Power Grid Design, Analysis and Verification
- Dynamic Power Reduction
- Leakage Power Reduction
- Reliability Analysis
- Noise Margin Analysis
- Advanced Delay Calculation & STA, including noise & coupling
(in ShowTime)
Availability
Sequence's new Zero-Sim power estimation feature for RTL is
currently available with PowerTheater. For additional product and
pricing information contact Sequence at sales@sequencedesign.com.
About Sequence
Sequence Design, Inc., the SoC Design Closure Company(SM), enables
system-on-chip designers to bring higher-performance and lower-power
integrated circuits quickly to tape out. Sequence's physical design
software and solutions give its more than 100 customers the
competitive advantage they need to excel in aggressive technology
markets, despite demanding complexity and time-to-market issues of
sub-180 nanometer designs.
Sequence has worldwide development and field service operations.
The company was formed through the merger of Sente, Inc., Sapphire
Design Automation, Inc. and Frequency Technology. Sequence is
privately held. Sequence is a member of Cadence Design Systems'
Connections(TM)and Mentor Graphics' Open Door(TM) partnership
programs. Additional information is available at sequencedesign.com.
Note to Editors: All trademarks mentioned herein are the property
of their respective owners.
Contact:
Sequence Design Inc.
Greg Fawcett, 408/961-2365
gfawcett@sequencedesign.com
or
Public Relations for Sequence
Jim Lochmiller, 541/552-0616
lochpr@yahoo.com
